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. 2016 Jan 28;23(Pt 2):395–403. doi: 10.1107/S1600577515022754

Figure 8.

Figure 8

Resolving CHESS bunch train patterns was demonstrated by synchronizing the framing of the detector with the ring, setting the frame times for successive integration periods to capture different bunches, and phasing 140 ns integration windows with the ring synchronization signal by increasing the delay signal, t delay. Shown are the output from the first five capacitors as a function of phasing (delay) time. Each capacitor output is sampled signal from different bunch trains.