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. 2016 Apr 12;6:24370. doi: 10.1038/srep24370

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Copyright © 2016, Macmillan Publishers Limited

This work is licensed under a Creative Commons Attribution 4.0 International License. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in the credit line; if the material is not included under the Creative Commons license, users will need to obtain permission from the license holder to reproduce the material. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

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Inline graphic — Phase boundaries (PB) are marked in green lines and Burgers circuits in yellow lines. (a) a two-layer step, (b) a four-layer step, (c) a six-layer step, (d) an eight-layer step. The original images corresponding to (a–d) are in Fig. S6.

Phase boundaries (PB) are marked in green lines and Burgers circuits in yellow lines. (a) a two-layer step, (b) a four-layer step, (c) a six-layer step, (d) an eight-layer step. The original images corresponding to (a–d) are in Fig. S6.