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. Author manuscript; available in PMC: 2016 Apr 22.
Published in final edited form as: IEEE Trans Nucl Sci. 2016 Jan 11;63(2):620–629. doi: 10.1109/TNS.2015.2499600

Fig. 5.

Fig. 5

Simplified Standard System architecture. An analog detector signal is passed through the analog front end (AFE) for filtering, timestamping, and digitization. Then it is processed using real-time algorithms on the DB’s FPGA and handed over to an IO FPGA for multiplexing. Finally it is given to the main FPGA for correlation and combination. A DU packs the formatted data and passes it to its parent chassis.