Table 1.1.
General | |
Form factor | 6U VME |
Input power supply | +3.3V, +5V, −5V |
Analog Input | |
Number of channels | 16 |
Input voltage range | −0.8 to 0 V |
Input impedance | 50 ohm single-ended |
Input bandwidth | 1.8 GHz |
Anti-aliasing filter bandwidth | 7 MHz |
Analog-to-Digital Conversion | |
Sampling speed | 10 to 65 MSPS |
Resolution | 12 bits |
Energy resolution | < 2 keV |
Timing Characteristics | |
High-resolution FPGA-based TDC | < 30 ps LSB |
Timing resolution | < 100 ps fwhm |
Front Panel Digital I/O | |
Number of inputs | 4 LVDS pairs |
Number of outputs | 4 LVDS pairs |
Memory | |
SRAM | 2 MB |
FLASH | 8 MB |
Backplane Digital Bus I/O | |
Maximum clock speed | 80 MHz |
Number of slow communication lines | 4 LVTTL |
Number of data output lines | 16 LVDS pairs |