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. Author manuscript; available in PMC: 2016 Apr 29.
Published in final edited form as: J Instrum. 2015 Aug 12;10:T08002. doi: 10.1088/1748-0221/10/08/T08002

Table 1.1.

Specifications of the 16-channel Detector Board

General
 Form factor 6U VME
 Input power supply +3.3V, +5V, −5V
Analog Input
 Number of channels 16
 Input voltage range −0.8 to 0 V
 Input impedance 50 ohm single-ended
 Input bandwidth 1.8 GHz
 Anti-aliasing filter bandwidth 7 MHz
Analog-to-Digital Conversion
 Sampling speed 10 to 65 MSPS
 Resolution 12 bits
 Energy resolution < 2 keV
Timing Characteristics
 High-resolution FPGA-based TDC < 30 ps LSB
 Timing resolution < 100 ps fwhm
Front Panel Digital I/O
 Number of inputs 4 LVDS pairs
 Number of outputs 4 LVDS pairs
Memory
 SRAM 2 MB
 FLASH 8 MB
Backplane Digital Bus I/O
 Maximum clock speed 80 MHz
 Number of slow communication lines 4 LVTTL
 Number of data output lines 16 LVDS pairs