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. Author manuscript; available in PMC: 2017 Jan 13.
Published in final edited form as: Chem Rev. 2015 Dec 21;116(1):215–257. doi: 10.1021/acs.chemrev.5b00608

Figure 5.

Figure 5

(a) A typical planar FET. The semiconductor substrate (e.g., p-Si) is connected to gate (G), source (S) and drain (D) electrodes, and can be switches between the “off” and “on” states by applying the Vg. (b) Schematic and SEM image of a NW-FET. Reprinted with permission from Ref. 175. Copyright 2002 American Chemical Society. (c, d) Transistor characteristics of p- and n-type NWs. Insets show transfer characteristics of the back-gated devices. (c) Reprinted with permission from Ref. 135. Copyright 2004 American Chemical Society. (d) Reprinted with permission from Ref. 179. Copyright 2004 John Wiley & Sons, Inc.