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. Author manuscript; available in PMC: 2017 Mar 22.
Published in final edited form as: ACS Nano. 2016 Feb 22;10(3):2995–3014. doi: 10.1021/acsnano.5b03299

Figure 4.

Figure 4

Throughput (m2·s−1) versus cost ($·m−2) for top-down patterning techniques used in integrated circuit manufacturing. Despite nine orders of magnitude variation in cost and throughput, each technique falls into the nanomanufacturing, rather than nanofabrication, category in this context. While not capable of the same performance in terms of placement accuracy, roll-to-roll nanoimprint lithography is included as a point of comparison with another high-throughput nanoscale patterning technique. Note the strong negative correlation between throughput and cost.