Figure 4. Top gate field-effect transistor fabricated on graphene on diamond.

(a) Two terminal current–voltage characteristics I_ds versus V_ds at zero gate bias. (b) Three-terminal measurement source-drain current versus top-gate bias. Drain voltage is fixed at 0.1 V. Scale bar, 100 μm. The dark part is a dielectric layer of HfO₂ with the size of 200 μm by 300 μm. The gate electrode is 200 μm in width and 120 μm in length. The source and drain electrodes are 200 μm in width and 50 μm in length.