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. Author manuscript; available in PMC: 2016 Aug 18.
Published in final edited form as: IEEE J Solid-State Circuits. 2016 Feb 2;51(3):697–711. doi: 10.1109/JSSC.2016.2517133

Fig. 8.

Fig. 8

Simulated capacitance of each delay cell in CSRO, CERO, and hCERO.