. Author manuscript; available in PMC: 2016 Aug 18.

Published in final edited form as: IEEE J Solid-State Circuits. 2016 Feb 2;51(3):697–711. doi: 10.1109/JSSC.2016.2517133

Tabel I.

Performance Summary and Comparison to Other Prior Works

	This work		CSRO	[17]	[18]	[19]	[20]	[21]	[22]	[23]	[24]
	CERO	hCERO	CSRO	[17]	[18]	[19]	[20]	[21]	[22]	[23]	[24]
Process (nm)	180			350	350	180	800	180	600	180	130
V_dd (V)	1.8			3.3	3.3	2	5	3.3	3.0	1.8	1.2
f_MAX (Hz)	60 M	61 M	113 M	256 M	1.1 G	807 M	407 M	368.9 M	366 M	6.9 G	10 M
f_MIN (Hz)	1.2	2.3	74	4.8	4k	20 M	13	40	40	75 M	1.75 k
log (f_MAX / f_MIN)	7.7	7.4	6.2	7.7	5.4	1.6	7.5	7.0	7.0	2.0	3.8
Power @ f_MAX (W)	44 μ	23 μ	23 μ	1.76 m	N/A	N/A	29.2 m	30.05 m	70 μ	9.32 m	3.6 μ
Power @ f_MIN (W)	5.1 p	6.4 p	247 n	N/A	N/A	N/A	N/A	N/A	70 μ	70 μ	1 μ
EpC @ f_MAX (J/cycle)	0.73 p	0.38 p	0.20 p	6.88 p	N/A	N/A	71.7 p	81.5 p	0.19 p	1.35 p	0.36 p
EpC @ f_MIN (J/cycle)	4.25 p	2.78 p	3.34 n	N/A	N/A	N/A	N/A	N/A	1.75 μ	0.93 p	0.57 p
Comments	Silicon measurement						Spice simulation