Fig. 2. Electrical properties of CNT array FETs and influence of postdeposition treatment on conductance.

(A) I_DS-V_GS curves forward sweep for a representative “rinsed + annealed” FET with L_ch = 100 nm where the open and filled symbols are plotted on linear and logarithmic scales, respectively. (B) I_DS-V_DS output curves for the same device as in (A). (C) G_on versus L_ch obtained from CNT arrays that have undergone the three different postdeposition treatment conditions, fit to Eq. 1, with a sevenfold total increase in G_on resulting from the “rinsed + annealed” treatment. (D) g_m versus L_ch for each surface treatment fit to ${\mathit{g}}_{\mathrm{m}}\propto {\mathit{L}}_{\text{ch}}^{-1}$ as a guide to the eye, with a threefold total increase in g_m resulting from the “rinsed + annealed” treatment.