Figure 2. AND logic demonstrated in a two-gate IZO-based EDL transistor using GO/chitosan composite as gate dielectrics.

(a) Schematic of IZO-based EDL transistor using inorganic/organic GO/chitosan composite film as gate dielectric (Drawn by C.W.). G₁ and G₂ are lateral gates. (b) Aging tests of the transfer curve measured by sweeping the bottom gate voltage. (c) The transfer curves measured by sweeping the voltage on lateral gate G₂ can be tuned by G₁. (d) AND logic operation using two lateral gates as inputs. During measurements, 0 and 1 denote the voltages of −1.0 and 1.0 V, respectively.