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. Author manuscript; available in PMC: 2017 Sep 11.
Published in final edited form as: Nucl Instrum Methods Phys Res A. 2016 May 24;830:119–129. doi: 10.1016/j.nima.2016.05.085

Figure 1.

Figure 1

(a) A strip-line board (SLB#1). A linear array of eight LYSO scintillators is coupled to 8 SiPMs on a strip-line on the board. (b) The numbering of SiPMs on a strip-line and PDRS4 readout channel assignment. (c) A schematic diagram shows the biasing scheme for a buffer transistor (ROHM 2SC5662). Two strip-line boards are used in this work and the strip-line bias is 0 V for SLB#1 and 0.6 V for SLB#2. (d) The output capacitance vs. bias voltage for the 2SC5662 transistor across the collector and base [24].