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. 2016 Nov 22;113(50):14261–14266. doi: 10.1073/pnas.1606947113

Fig. 5.

Fig. 5.

FT-FET-PLED integrated devices. (A) Schematic illustration of the FT-FET-PLED device structure. (B) Photographs of FT-FET-PLED devices with different emissive layers: PDY-132 (yellow), SW-111 (white), MEH-PPV (red), and F8BT (green). The photographs show the PLEDs being driven by the integrated FETs during bending. (C) The L of the yellow FT-FET-PLED device and the IDS supplied to the PLED by the integrated FET as a function of VGS. The driving voltage (VDS) is fixed at −60 V. For the integrated FET, the channel length and width are 50 μm and 38 mm, respectively. (D) EL spectra of normal yellow PLED and integrated yellow FT-FET-PLED devices. (E) L-VGS characteristics of FT-FET-PLED devices with various emissive layers. VDS is fixed at −60 V.