Table 1.
Register and LUT resources needed for the implementation of the architecture in Figure 5A on Spartan6-LX150 FPGA.
| Block name | Registers | LUTs | 18-kb block RAM elements |
|---|---|---|---|
| Neuron core/top layer (×1) | 520 | 915 | 0 |
| Neuron core/input and hidden layer (×15) | 35 × 15 | 225 × 15 | 1 × 15 |
| PRNG (×1) | 58 | 19 | 0 |
| Central controller (×1) | 627 | 1413 | 0 |
| DDR2 memory controller (×1) | 263 | 411 | 0 |
| USB monitor and setup (×1) | 2778 | 2999 | 1 |
| Total | 4,771 (1%) | 9,123 (3%) | 16 (6%) |
The percentage utilization for each resource is shown in the bottom row.