Figure 2.

Simplified fabrication process: (a) Parylene C coating on a silicon wafer; (b) Patterning discontinuous holes on parylene; (c) XeF2 etching to completely undercut the handling wafer and form underlying channels; (d) 2nd parylene deposition to seal the previously opened parylene windows; (e) Ti/Au deposition to form electrodes/traces/pads; (f) 3rd parylene layer to insulate the metal layer; (g) Patterning the parylene layer; (h) Backside DRIE etching to release the device from silicon wafer; and (i) Insertion of the Ag/AgCl wire and sealing of the tip with agarose gel.