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. Author manuscript; available in PMC: 2017 Dec 11.
Published in final edited form as: J Mater Chem C Mater. 2015 Apr 27;3(25):6445–6470. doi: 10.1039/C5TC00755K

Fig. 10.

Fig. 10

Device fabrication and electrical performance. (a) Schematic after anisotropic etch. The silicon-on-insulator active channel (yellow, width w and thickness t) is undercut etched, whereas degenerate leads (red) are etch resistant. The source (S), drain (D), and underlying back gate (G) are labelled. (b, c) Scanning electron micrograph (b) and optical micrograph (c) of a completed device. (d) ISD (VSD) (w = 50 nm, t = 25 nm) for varying VGS (0 to −40 V, ΔV = −1 V), illustrating p-type accumulation mode behaviour. (e) |ISD|(VGD) for VSD = 1 V for forward (red) and reverse (black) sweep. (f) Accumulation-mode Hall and drift mobilities versus temperature (w = 300 nm, t = 25 nm). Copyright Nature, Nature Publication Group.131