Table III. State-of-the-art VP Signal Processors.
| This work1 | Johns Hopkins [4, 36] | Imperial / UCY2 [5, 37, 38] | CLONS3 [6] | ETH Zürich / Scuola Superiore [7] | |
|---|---|---|---|---|---|
| Technology | ASIC (TI 0.35μm CMOS) | Commercial μcontroller | ASIC (AMS 0.35μm CMOS) | Commercial Signal Processing Platform | Hybrid analog and digital off-the-shelf and ASIC components |
| Functionsa | CST (3 SCCs or 2 otoliths) ND+FM (2 SCCs and 1 otolith) | CST+ND+FM+AM (3 SCCs) | ND+AM (3 SCCs and 2 otoliths) | CST+ND+FM+AM (3 SCCs) | ND+FM (3 SCCs and 2 otoliths) |
| Area | 6.22 mm2 | 81 mm2 | 1.19 mm2 | 8202 mm2 | Not reported |
| Power | 1.24 mW | 12 mW | 53.8 μW (1 SCC and 1 otolith) | Not reported | Not reported |
1
Bias voltages and currents are generated externally. The processor does not include digital circuit blocks necessary for programming (e.g., memory elements, D/A converters).
2
Measurement results for the SCC processor are not reported.
3
The system is not designed as a prosthetic device but as a research development platform. The area of the system is presented for the sake of completeness.
a
CST: Coordinate System Transformation, ND: Neural Dynamics, FM: Frequency Modulation, AM: Amplitude Modulation