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. Author manuscript; available in PMC: 2019 Feb 13.
Published in final edited form as: Lab Chip. 2018 Feb 13;18(4):639–647. doi: 10.1039/c7lc01113j

Fig. 5.

Fig. 5

(a) 11 × 11 interconnect array test set up. (b) Composite image from four Zeta-20 microscope images of fabricated 11×11 array of SIMs. Close up shows details of SIMs, including slight pixelation of the sealing surface. (c) Pressure as a function of time for the test set up in (a) repeated 100 times.