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. 2018 Mar 9;8:4251. doi: 10.1038/s41598-018-22634-w

Figure 4.

Figure 4

The structure of phase retarder 1 and phase retarder 2 using an FLC, (a) when the FLC phase retarder is subject to an applied voltage of −10 V and (b) +10 V. (c) The structure of phase retarder 3 using nematic LC when the voltage is switched off. (d) The phase retardation of phase retarder 3 as a function of applied voltage.