. Author manuscript; available in PMC: 2019 Apr 1.

Published in final edited form as: IEEE Trans Circuits Syst Video Technol. 2016 Nov 18;28(4):1021–1036. doi: 10.1109/TCSVT.2016.2630848

TABLE II.

FPGA Prototype Resource Consumption

FPGA Resource (Zedboard Zynq-7020)	Slice LUT	Slice Register	Total Slice	Block RAM	DSP (Multiplier/MAC)	BUFGCTRL (Clocking)
Temp. Gabor Filter Array	20353	15862	7277	0	0	0
Spatial Gabor Filter Array	5788	2023	1736	0	84	0
Motion Energy Extract. Array	5005	4128	1596	0	21	0
Velocity Voter Array	2415	4637	1070	0	42	0
WTA	847	2724	727	0	0	0
Parameter Register Bank	4965	5544	2583	0	0	0
Other Modules	4552	570	-	31.5	0	1
Total	43925/53200 (82.6%)	35488/106400 (33.4%)	12597/13300 (94.7%)	31.5/140 (22.5%)	147/220 (66.8%)	1/32 (3.1%)