Figure 6.

(a) Schematic diagram of the device structure comprising a graphene PD with a pentacene light absorption layer and an Au NP charge trapping layer. In the device, the ITO acts as a gate electrode and Au as source/drain electrode; (b) Photographic image of the graphene PD fabricated on a PEN substrate; (c) Photoresponsivity and photodetectivity vs. illumination power; (d) Two-dimensional spatial profile of |E²| of the hybrid PD with or without Au NPs; (e) Retention time and (f) cycling tests of the graphene PD with a memory functionality under various illumination powers. Reproduced with permission for Figure 6a–f from 2015 Nano Letters [72].