Table 2.
Operational sequence of the demonstrative instructions
| Mnemonic | Effect | T0 | T1 | T2 | T3 | T4 |
|---|---|---|---|---|---|---|
| MOVA | ACC ← Memory | IR ← Memory | PC ← PC + 1 | ACC ← Memory | PC ← PC + 1 | |
| ADD A | ACC ← ACC + A | IR ← Memory | PC ← PC + 1 | A ← Memory | PC ← PC + 1 | ACC ← (A + ACC) |
| SUB A | ACC ← A-ACC | IR ← Memory | PC ← PC + 1 | A ← Memory | PC ← PC + 1 | ACC ← (A-ACC) |
| OUT A | Memory←ACC | PC ← PC + 1 | IR ← Memory | PC ← PC + 1 | Memory←ACC | |
| HLT | STOP | |||||