Fig. 1. Tuning graphene conductivity with a low gate voltage bias.

a Schematic of the FET structure in which a-Si serves as part of the back-gate electrode and the ultrathin Al₂O₃ layer serves as the gate dielectric. b Measured drain-source current I_ds across the graphene as a function of gate voltage V_g at different drain-source biases V_ds. c Graphene resistance R_ds as a function of gate voltage at V_ds = −0.50V, revealing the graphene charge neutrality point at approximately 2 V