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. 2018 Sep 13;8:13727. doi: 10.1038/s41598-018-31958-6

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© The Author(s) 2018

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.

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(a) The structure of tunable memristive neuron. When there is an input pulse, the resistance of memristor will decrease. V_read is divided by memristor and MOSFET and V₀ is the voltage between two terminals of MOSFET. When there is a rising edge of read clock, the D-Latch will read the V₀. If V₀ reaches the threshold of D-Latch (V_DL), the output of D-Latch will change to a high level. Then the reset circuit will work. When the falling edge of the read clock is coming, the memristor and the output of D-Latch will be reset. (b) The sequence diagram of memristive neuron. (c) The TEM image of the HfO_x-based memristor. (d) The relationship between V₀ and input pulse number under different gate potentials. The higher gate potential, the harder for V₀ to reach V_DL. (e) The relationship between the gate potential (V_th) and input pulse number when there is one output spike. When the V_th lower than 400 mV, the relationship will nearly be a constant, we deem that three input pulses can trigger an output spike.