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. 2018 Feb 26;4:1. doi: 10.1038/s41378-018-0004-7

Fig. 2. Cross-sectional schematics and scanning electron microscope images of fabrication procedure.

Fig. 2

a Pores are defined with interference lithography and etched into a silicon-on-insulator (SOI) wafer. b Microchannels are defined with projection photolithography and etched into a silicon wafer. c These two wafers are fusion bonded together and then deep reactive ion etching is used to open the back side of the SOI wafer for vapor to exit.