Fig. 1.
a Optical and b FE-SEM images of p-type Si NW FET devices; c four probe measurements and d hysteresis behaviors for a back-gate Si NW FET during the gate voltage scan from +5 to −5 V, +10 to −10 V, and back
a Optical and b FE-SEM images of p-type Si NW FET devices; c four probe measurements and d hysteresis behaviors for a back-gate Si NW FET during the gate voltage scan from +5 to −5 V, +10 to −10 V, and back