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. 2018 Oct 24;18(11):3605. doi: 10.3390/s18113605

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© 2018 by the authors.

Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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(i) Steps to fabricate ultra-thin silicon based PVDF-TrFE capacitors: (a) Hard mask growth (b)Backside patterning to open etching window (c) Bottom metal deposition and patterning (d) PVDF-TrFE spin coating, annealing and top metal deposition (e) Patterning top metal and dry etching of polymer (f) Wet etching of bulk silicon (g) Final device on thin silicon (ii) (top) Scanning Electron Microscopy image of the piezo-capacitor sensor (bottom) optical profilometer image showing warp image of thin chip with the piezo-capacitor. Reprinted with permission from [110] © 2016 Elsevier.