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. 2019 Jan 3;10:54. doi: 10.1038/s41467-018-07904-5

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© The Author(s) 2019

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.

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Fig. 6 — 3D NAND digital circuit design based on stacked 3-T dual-gate devices. a Schematic circuits of a conventional NAND gate and a proposed 3D NAND gate. b DC V_OUT–V_IN characteristics of a 3D NAND gate. c 3D NAND array-based logic design (scale bar is 2 mm). d DC V_IN–V_OUT characteristics of a 1-input NOT gate and 2-input (A and B) logic gates (OR, AND, NOR, XOR, and XNOR) implemented by interconnecting 3D NANDs. A fixed voltage (0 or 5 V) is applied to one port while a voltage input on the other port is swept. e A large-scale flexible logic circuitry implemented by using a 12 × 8 3D NAND gate array (scale bar is 4 mm)