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. 2019 Jan 3;10:54. doi: 10.1038/s41467-018-07904-5

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© The Author(s) 2019

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.

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Fig. 8 — Mechanical, electrical, long-term, and environmental reliabilities a Images of the stacked 3-T device under bending test (white dotted area is magnified) and its saturation transfer characteristics as bent on a curved surface (scale bars in the top and bottom images are 1 cm and 1 mm, respectively). b Shift of the saturation transfer characteristics of the printed stand-alone complementary transistors after electrical bias stress for 10,000 s (at V_GS = V_DS = 5 V for the n-type and −5 V for the p-type). c Year-long observation on the carrier mobilities and threshold voltages of the stand-alone and stacked 2-T devices (μ_n, μ_p: carrier mobility, μ_n0, μ_p0: initial carrier mobility, V_TH,n, V_TH,p: threshold voltage, error bars represent standard deviation). d Shift of the saturation transfer characteristics of the complementary dual-gate transistors under consecutive five thermal stress steps. e Shift of the saturation transfer characteristics of the complementary dual-gate transistors under a humid environment (90% rh, 30 °C) for 24 h (rh: relative humidity)