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. Author manuscript; available in PMC: 2019 Jul 1.
Published in final edited form as: IEEE Trans Circuits Syst II Express Briefs. 2017 Jul 12;65(7):839–843. doi: 10.1109/TCSII.2017.2725988

Table I.

Design Parameters of Analog Front-End

P1, P2(W/L) N1, N2(W/L) C1/C2 C3/C4 CL
175 μm/3 μm 400 μm/2 μm 30 pF /200fF 2 pF
/50 fF~850 fF		 5 pF