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. Author manuscript; available in PMC: 2019 Jun 1.
Published in final edited form as: IEEE J Emerg Sel Top Circuits Syst. 2018 Mar 5;8(2):221–229. doi: 10.1109/JETCAS.2018.2812105

Fig. 5.

Fig. 5

The flow chart presents the back-end module processes receiving packets from the front-end in recording mode, switches to transmitting to send stimulation instructions and restarts the loop.