Table 1.
Ref. | Institution | Switch Engines | Scalability & Topology | On-chip Insertion Loss (dB) | Coupling Loss (dB) | Crosstalk (dB) | Switch Time | Power (W) | Size (mm2) |
---|---|---|---|---|---|---|---|---|---|
[68] | NEC | T-O MZI | 8 × 8 PILOSS | - | - | −25 | - | - | 12 × 3 |
[69] | 8 × 8 Switch & select | 4 | 1 | −35 | 150 μs | 12 × 14 | |||
[28] | Bell Labs | 8 × 8 Switch & select | 4 | 3.5 | −30 | 250 μs | 0.07 | 8 × 8 | |
[70,71] | AIST | 32 × 32 PILOSS | 8.4 | 1.4 | −35 | 30 μs | 1.9 | 25 × 11 | |
[72] | IBM | E-O MZI | 4 × 4 | 3.7 | - | −15 | 5 ns | 0.05 | 0.165 |
[73] | 8 × 8 Double Layer | - | - | - | - | 0.675 | |||
[41] | SJTU | 16 × 16 Benes | 14 | 5 | −10 | 3.2 ns | 1.2 | 10.7 × 4.4 | |
[74] | CAS | T-O MZI | 32 × 32 | 18.5 | 5 | −15 | 1.2 ns | 0.54 | 12.1 × 5.2 |
[75] | E-O MZI | 64 × 64 Benes | 12 | −30 | - | - | 21.7 × 9.6 | ||
[76] | Huawei | T-O MZI | 32 × 32 | 13 | 3.2 | −20 | 1.4 ms 70 μs |
1 20 |
12 × 12 |
[77] | 16 × 16 Hybrid Dilated Benes | 22 | 4.5 | - | - | - | 12.5 × 12.5 | ||
[44] | HKUST | E-O MRR | 5 × 5 Cross-bar | - | - | −11 | 1.3 ns | - | 0.1 × 0.1 |
[78] | TU/e | T-O MRR | 8 × 7 Cross-bar | 22 | 6 | −20 | 17 μs | - | - |
[79] | CAS | 4 × 4 | - | - | −13 | 25 μs | - | - | |
[80] | Ericsson | 48 × 8 Cross-bar | ~3 | 3.2 | −23 | 4 μs | - | 8.4 × 7.8 | |
[81] | Columbia University | T-O MRR | 8 × 8 Switch & select | 10 | - | −39 | 20 μs | - | - |
[63] | UC | MEMS | 64 × 64 | 3.7 | 6.5 | −60 | <1 μs | 40V | 8.6 × 8.6 |
[82] | Berkeley | 128 × 128 Cross-bar | 22.7 | - | 25V | 16 × 17 |