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. 2017 Apr 10;3:17002. doi: 10.1038/micronano.2017.2

Figure 1.

Figure 1

(a) Interface pyramid showing the components in a conventional package, along with the estimated CTEs of the involved substrates. (b) Introducing a rigid 3D TSV interposer (right) to bridge the mismatch of the CTE values of the PCB board and the Si application-specific integrated circuit (ASIC) dies3. CTE, coefficients of thermal expansion; PCB, printed circuit boards; 3D TSV, three dimensional through silicon via.