Scheme 1.

(A-F) Schematic description of each step of the DEP cell trapping and lysis process. (A) Pretreat the device with Pluronic F-127 solution and incubate at 4 °C overnight to effectively inhibit cell adhesion on PDMS surface; (B) Fill the device with low conductivity DEP (LEC) buffer; (C) Trap single cells at the inlet of each chamber with optimized AC voltage and frequency; (D) Turn off the trapping voltage and inject fresh LAMP reaction buffer to flush away the excess cells and dispense the trapped cells into the chambers; (E) Fill the channel with the immiscible phase to compartmentalize cells in chambers; (F) Lyse cells and initiate single-cell LAMP analysis; (G) Schematic of the SD DEP chip showing the dimensions of the key features.