Table 1.

Cache misses for DL distance algorithms, in millions, on Xeon4

A	B	DL	LS_DL	Strip_DL	L vs D	S vs D	S vs L
40000	40000	201	265	6	-31.8%	97.5%	97.9%
80000	80000	1267	715	16	43.6%	98.8%	97.8%
120000	120000	4006	2180	42	45.6%	99.0%	98.1%
160000	160000	**	10,652	63			99.4%
200000	200000	**	19,751	147			99.3%
240000	240000	**	24,257	133			99.5%
280000	280000	**	38,119	188			99.5%
320000	320000	**	44,815	242			99.5%
360000	360000	**	61,296	1352			97.8%
400000	400000	**	160,118	2407			98.5%

^** ⇒ insufficient memory