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. 2019 May 10;9(5):727. doi: 10.3390/nano9050727

Figure 10.

Figure 10

Plots for (a) 20 cycles of repetitive I–V measurements of square-overlap layout devices having spacer thickness of 4nm, and I–V measurements of square-overlap devices over five different areas on a 4-inch Si wafer having spacer layer thicknesses of (b) 4 nm, (c) 5 nm, and (d) 6 nm.