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. Author manuscript; available in PMC: 2019 Jul 12.
Published in final edited form as: IEEE J Solid-State Circuits. 2017 Oct 16;52(11):2843–2856. doi: 10.1109/JSSC.2017.2749425

Fig. 5.

Fig. 5

System floor plan with data path and clock distribution (area not drawn to scale).