Fig. 1.

a Schematic of IGZO transistor array devices. The inset shows an optical microscope image of a single IGZO device with a channel region (50 μm length and 500 μm width). Transfer characteristics (drain current–gate voltage of I_D–V_G) of b reference IGZO transistor without post-annealing and d IGZO transistor with post-annealing at variable V_D (0.1, 0.5, and 2 V). Output characteristics (I_D–V_D) of c reference IGZO transistor and e IGZO transistor with post-annealing at variable V_G from 0 to 2 V