Figure 1.

The all-SiC fabrication process flow. (a) A rendering of the Michigan-style 3C-SiC probe. The process flow inside the red rectangle shows the cross-section at the electrode sites while the blue rectangle provides the cross-section at the contact pads on the tab. (b) Starting SOI wafer, (c) ~8 µm of p-type 3C-SiC was grown on top, followed by ~2 µm of heavily n-type (n⁺) 3C-SiC. (d) The wafer was coated with photoresist and (e) patterned via photolithography. (f) DRIE process was used to form the conductive n⁺ mesas and (g) a thin a-SiC insulating layer was deposited on top via PECVD. (h) Photoresist was then patterned with photolithography and (i) the a-SiC was etched to form windows for the electrode sites using a RIE process. (j) After the a-SiC windows were opened, a layer of titanium, followed by gold, was deposited on the contact pads and thermally annealed. A deep DRIE etch through both epi layers and the oxide was performed to (k₁) define the probes and (k₂) form through-holes in the contact pads. (l₁, l₂) The oxide layer was etched in HF (49%) to release the probes. (m₁, m₂) Back-thinning via DRIE was performed to remove the residual silicon from the SOI device layer.