Figure 5.

(a) The schematic diagram of the contents layers of 0.35 μm CMOS Bio-MEMS process. In this schematic, metal layers (M₁-M₄) are the layers for electronic circuit layout routing, Via₁-Via₃ are the interconnection between adjacent metal layers, and inter-metal dielectric layers (IMD₁-IMD₃) are the dielectric layers used to electrically insulate interconnect lines. (b) The images of the fabricated chip and the SEM picture of the fabricated electrodes and interconnections array. The yellow dash square represents the double –size width designed of contact points between Ti/Au and M₄ layers.