Fig. 3.
Logic gates based on printed electrochemical transistors. Schematics of an inverter (a) and a two-input NAND gate (b) based on OECTs, together with the corresponding optical images (scale bar: 1 mm). The supply voltages VDD and VSS were +5 V and −5 V, respectively. c Voltage transfer characteristics and d switching characteristics of the inverter, where the propagation delay tp = 54 ms. e Characterization of the two-input NAND gate, where the propagation delay tp = 20 ms. f A four-input NAND gate according to the previous design (ref. 39) requires an area of ~150 mm2, partially owing to the relatively large area required for the resistor ladder. Microscope images of a portion of the four-input NAND gate (scale bar: 1 mm) and an electrolyte pattern printed with a low-resolution screen mesh (scale bar: 0.5 mm) are also shown, for comparison with the new design. g The four-input NAND gate according to the new design only requires an area of ~12.5 mm2, which corresponds to a footprint reduction by a factor of ~12. This footprint reduction is explained by shrinkage of the resistor ladder area and utilization of high-resolution screen meshes. The four-input NAND gate manufactured according to the new design fits within the area of the microscope image (×2.5 magnification), whereas only one OECT, R2, and R3 from the previous design fit within the same microscope image area (scale bar: 1 mm). In addition, the resistor ladder printed according to the new design is much more well-defined, which results in reproducible voltage output levels owing to higher matching accuracy between R1, R2, and R3. The rightmost microscope image shows an electrolyte pattern printed with a high-resolution screen mesh, which results in well-defined printed features allowing for narrower design rules, further footprint reduction and improved manufacturing yield (scale bar: 0.5 mm)