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. 2019 Dec 10;16:156. doi: 10.1186/s12984-019-0629-2

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© The Author(s). 2019

Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The Creative Commons Public Domain Dedication waiver (http://creativecommons.org/publicdomain/zero/1.0/) applies to the data made available in this article, unless otherwise stated.

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Fig. 4 — Structure of the proposed instrument. The instrument’s architecture includes: (a) a high-performance, eight-channel (five channels on the main board and another three channels on a stacked PCB that is adjusted on the two headers shown in the picture) AFE, (b) an analog, low-power 3-axis accelerometer, (c) an eight-channel, 24-bit ADC, (d) an FPGA module, (e) a 2 MBps Zigbee transceiver, and (f) a 2.4 GHz antenna