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. 2019 Dec 20;5(12):eaax6061. doi: 10.1126/sciadv.aax6061

Fig. 6. Simulated performance of optimized devices.

Fig. 6

(A) Simulated I-V characteristics of the device geometry used in our experiments, assuming no external series/shunt resistances. (B) Simulated VOC, JSC, fill factor (FF), and power conversion efficiency (PCE) for optimized devices. Apart from the final device geometry (“Optimized WS2 device”), optimizations are independent, not cumulative. (C) Simulated I-V characteristics of the fully optimized WS2 device.