Table 1.

Salient Features of different LIM techniques proposed in literature.

Ref	Building Block	Logic	Salient Features
10	BRSa and CRSb cells	Non-Statefulc V-R logic (sequential logic)	14 out of 16 Boolean function realized in maximum 3 cycles, retains logic output, destructive read operation
11	1 BRS	Non-Stateful V-R logic (sequential logic)	all 16 Boolean function realized in maximum 3 cycles, retains logic output, needs rectifying behavior
12	1 CRS	Non-Stateful V-R logic (sequential logic)	all 16 Boolean function realized in maximum 3 cycles, retains logic output, needs rectifying behavior
13	2 BRS (connected anti-serially)	Non-Stateful V-R logic (sequential logic)	all 16 Boolean function realized in max. 3 cycles, retains logic output
14	3 BRS	Statefuld R-R Logic	5 basic Boolean functions can be realized in 2 cycles, retains input variables and logic output
15	1T-1R	Non-Stateful V-R logic (sequential logic)	all 16 Boolean function realized in 2 cycles (+1 read cycle), retains input variables and logic output
16	3 BRS + passive resistor	Stateful R-R Logic	NAND, AND and other logics can be realized using different number of BRS devices or cascading, retains both input variables and logic output
17	3 BRS + passive resistor	Stateful R-R Logic	Boolean function except XOR and XNOR in 1 cycle, retains input variables and output
18	1R (4 resistance states) + passive resistor	Stateful R-R Logic	all 16 Boolean operations are realized, retains logic output
This Work	2T-1R or 1T-1R (R:4 resistance states)	Non-Stateful V-R logic	5 basic Boolean functions in 1 cycle, retains initial Memory state and logic output (not storing input variables)

^aBipolar restive switches, ^bComplementary resistive switches, ^cinput (voltage signal) and output (resistance) are in different forms, ^dinput and output are in the same form i.e. either both are voltage signals or recorded in terms of device resistance.