Table 3.

Measured LNA performance summary and comparisons.

Parameter	This Work		[13] (2019)	[18] (2018)	[16] (2016)	[11] (2015)	[17] (2015)
Topology	VA	CSA	VA	CFVA	TIA	VA	CFVA
Process technology	0.13 μm HV CMOS	0.13 μm HV CMOS	0.18 μm CMOS	0.18 μm HV-BCD	TSMC 0.18 μm HV CMOS	0.18 μm HV CMOS	0.18 μm CMOS
Transducer	PMUT	PMUT	PMUT	PZT	CMUT	PMUT	PZT
Power supply (V)	1.5	1.5	1.5	1.8	1.8	1.8	1.8
Power consumption (mW)	0.3	0.3	0.08	0.79	1.4	N/A	0.135
Area (10−4 mm2)	6	9	N/A	30 1	280	310	60
Voltage–voltage gain (dB)	21.8	N/A	29/30/42/53 2	18	N/A	N/A	−12/6/24
Transimpedance gain (dBΩ)	109.22 at 3 MHz	99.57 at 3 MHz	N/A	N/A	116/113.5 110/104	N/A	N/A
Bandwidth (MHz)	22	N/A	10	20	10.2/10.8 10.6/10.5	N/A	9.8
Input current noise (pA/√Hz)	0.08 at 3 MHz	0.15 at 3 MHz	N/A	N/A	0.41 @ 5 MHz	N/A	N/A
Input voltage noise (nV/√Hz)	7.1 at 3 MHz	N/A	N/A	7.9 at 5 MHz	N/A	11 at 0.22 MHz	5.9 at 4 MHz
Input dynamic range (dB)	69	71	90	75	N/A	N/A	81
FOMRX_1 (MHz/V2Aµm2)	16674	N/A	N/A	949	N/A	N/A	6633 3
FOMRX_2 (Hz/mA3µm2)	N/A	4.1*109	N/A	N/A	0.09*109 3	N/A	N/A

¹ This area was estimated from a chip micrograph. ² Including a TGC amplifier as a second stage. ³ Computed considering its higher gain.