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. 2020 Mar 13;14:143. doi: 10.3389/fnins.2020.00143

Table 4.

Overheads of an FPGA SNN with on-chip HM2-BP vs. ST-DFA-2 (Network size:196-100-100-10).

LUTs FFs DSPs Backward phase latency (uS)
HM2-BP 154477 23462 900 17.560
ST-DFA 126482 23331 210 12.010
Normalized LUTs (%) Normalized FFs (%) Normalized DSPs (%) Normalized B-P latency (%)
HM2-BP 122 101 429 146
ST-DFA 100 100 100 100