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. 2020 May 8;12(22):25125–25134. doi: 10.1021/acsami.0c03794

Figure 5.

Figure 5

(a) Device layout for the prepared FETs. (b) Optical microscopy image of the thin film coating the source/drain electrodes of an assembled FET. Scale bar = 20 μm. (c) Transfer and (d) output curves for an assembled FET with a channel length of 10 μm. Vds = 0.5 V for the transfer curve.