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. 2020 Jun 4;20(11):3189. doi: 10.3390/s20113189
BRAM Block RAM
BS Background Subtractor
CPU Central Processing Unit
DRC Design Rule Check
FN False Negative
FP False Positive
FPGA Field Programmable Gate Array
FPS Frame Per Second
GMM Gaussian Mixture Model
HW Hardware
I/O Input and Output
IP Intellectual Property
MoG Mixture of Gaussian
OS Operating System
SoC System on Chip
SoM System on Module
SW Software
TP True Positive
UIO userspace I/O