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. Author manuscript; available in PMC: 2021 Jun 1.
Published in final edited form as: IEEE Trans Biomed Circuits Syst. 2020 Feb 6;14(3):425–440. doi: 10.1109/TBCAS.2020.2972013

TABLE II.

Power consumption summary of the main blocks in the designed digital signal processor

Digital Signal Processor Mode-1 (640kHz) Mode-2 (80kHz)
Decimation Filter (μW) 15 2.5
Low-Pass Filter (μW) 5 1
High-Pass Filter (μW) 8 1.5
Hilbert Transform (μW) 12 2
Spike Probability Generator (μW) 8 1.5
Other Blocks (μW) 4 1
Total Power Consumption (μW) 52 9.5