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. 2020 Jul 3;11:3362. doi: 10.1038/s41467-020-17084-w

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© The Author(s) 2020

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.

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Fig. 3 — a Fabrication process. A water-soluble sacrificial layer was spin-coated on a Si/SiO₂ wafer followed by a PDMS-azide layer. A chemically orthogonal stretchable dielectric layer (PFPE-DMA) is spin-coated and UV cured. A stretchable conductor as the gate electrode is spray-coated through a shadow mask first with a mixture of CNT/poly(3,4-ethylenedioxythiophene) flowed by a PEDOT:PSS layer. Then a stretchable substrate made of PDMS is spin-coated. After curing, the entire structure is soaked in water and is released from the substrate and flipped over. Inkjet printing is used to pattern the stretchable semiconductor on the stretchable dielectric layer. Stretchable electrodes made of CNT/PEDOT:PSS are spray-coated through a shadow mask to give the source/drain (S/D) electrodes. b Optical microscopic images of a printed stretchable semiconductor pattern (red dashed box) on the PFPE-DMA dielectric film with stretchable CNT gate electrodes (black dashed box)and a fully stretchable transistors array with top CNT/PEDOT:PSS stretchable S/D contact electrodes (yellow dashed boxes) on the patterned semiconductors. c An optical photographic image of a fully stretchable 5 × 5 transistor active-matrix array. d Optical photographic images show the stretchable transistor array being subjected to 0% and 100% strain. e A representative transfer curve (V_d = −100 V) of the stretchable OTFT at 0% strain. f Distribution of the mobility from 16 devices on the fully stretchable OTFT array (Supplementary Fig. 8). g Changes in the saturation on-current and saturation mobility at gate voltage of −100 V and drain source voltage of −100 V with strains up to 100%, both parallel to (open circles) and perpendicular to (filled circles) the charge transport direction (n = 3). Values are mean ± S.D. h Changes in the saturation on-current and saturation mobility measured at gate voltage of −100 V and drain source voltage of −100 V after multiple stretching-releasing cycles (up to 1000 cycles) at 100% strain parallel to (open circles) and perpendicular to (filled circles) the charge transport direction.